In recent years, digital cameras etc. including built-in solid-state imaging apparatuses have been widespread. It has been known that, in the solid-state imaging apparatuses, when high-brightness light having certain brightness or more enters, a black part into which light does not seem to enter may appear in an image. Such phenomenon is hereinafter referred to as “blocked-up shadows.” As a technique for reducing or preventing the blocked-up shadows, the following technique (e.g., see Japanese Patent Publication No. 2009-177378 which is hereinafter referred to as “Patent Document 1”) is disclosed.
FIG. 16 is a view illustrating a configuration of a solid-state imaging apparatus 100 of Patent Document 1. Referring to FIG. 16, the solid-state imaging apparatus 100 of Patent Document 1 includes pixels 110, vertical signal lines 111, a constant current source 112, a noise canceller circuit (correlated double sampling (CDS) circuit) 113, horizontal signal lines 114, and an output AMP 115. The plurality of pixels 110 are arranged in a matrix as unit pixels.
The pixel 110 includes a photodiode PD configured to perform photoelectric conversion, a transfer transistor MTR, a reset transistor MRS, an amplifier transistor MSF, and a floating diffusion part FD (hereinafter also referred to as an “FD part”) configured to store charge.
First, the blocked-up shadows will be described. The voltage Vfd of the FD part drops due to entering of high-brightness light, and the potential Vpixout of the vertical signal line drops to equal to or lower than a permissible minimum value. As a result, even if signal charge is transferred from the photodiode PD to the FD part, the potential Vpixout cannot further drop. Thus, the blocked-up shadows occur.
The blocked-up shadows will be further described below with reference to FIG. 16 and a timing chart of FIG. 17. FIG. 17 is the timing chart illustrating a relationship among drive pulses in the solid-state imaging apparatus of Patent Document 1. In this case, a pixel from which an optical signal is read is a pixel 110<i>. 
When high-brightness light enters a pixel region, the voltage Vfd at the floating diffusion part FD may drop to a permissible minimum value (floating diffusion part minimum voltage Vfdmin) during the period from the point at which a reset pulse φRS<i> is changed to a low level to the point at which a transfer pulse φTR<i> is changed to a high level. In such a case, the potential Vpixout of the vertical signal line also drops to a permissible minimum value (pixel output minimum voltage Vpixoutmin).
This is because of, e.g., the following reason: charge is generated not only at the photodiode PD but also at the FD part due to leakage of intense light into the FD part; or charge generated at the photodiode PD leaks into the FD part.
In the foregoing state, even if signal charge dependent on light is transferred to the FD part with the transfer pulse φTR<i> being changed to the high level, the voltage Vfd at the FD part cannot fall below the FD part minimum voltage Vfdmin.
Thus, the pixel output voltage Vpixout does not fall below the pixel output minimum voltage Vpixoutmin, and therefore the difference ΔVpixout(sig) between reset voltage and signal voltage is 0 (ΔVpixout(sig)=Vpixoutmin−Vpixoutmin=0). Finally, horizontal signal line optical signal voltage ΔVout(sig)=0.
As a result, at a place where high-brightness light having certain brightness or more enters, a black image is formed as if no light enters.
In order to reduce the blocked-up shadows, various suppressor circuits have been proposed. The following has been known as one of the suppressor circuits. For the pixel 110<i> from which an optical signal is read, clip voltage for reducing or preventing the blocked-up shadows is generated from an adjacent pixel 110<i+1>, and the pixel output voltage Vpixout is clipped.
Such a case will be described with reference to the timing chart of FIG. 17.
First, a power supply pulse φVdd<i> is changed to a reference reset pulse φVddr, and the reset pulse φRS<i> is changed to the high level. This sets FD part voltage Vfd<i> at reference reset voltage Vddr. Moreover, in order to clamp the reset voltage to the CDS circuit 113, a clamp pulse φCL and a sample-hold pulse φSH are changed to the high level.
Next, a power supply pulse φVdd<K> connected to a non-selected pixel 110<K> (not shown in FIG. 16) other than the reading pixel 110<i> and the clipping pixel 110<i+1> is set at non-selected pixel voltage Vddl which has a value lower than the minimum value Vpixoutmin for an optical signal flowing through the vertical signal line 111, and FD part voltage Vfd<K> of the non-selected pixel is set at the non-selected pixel voltage Vddl.
Then, the reset pulse φRS<i> is changed to the low level.
Thus, due to a kTC noise (reset noise) component Vktc<i> at a reset transistor MRS<i>, field-through voltage Vft<i>, and gate/source voltage Vgs<i> at an amplifier transistor MSF<i>, pixel output voltage Vpixout<i>is changed to reset voltage Vrst<i> (=Vddr−Vnoise<i>−Vgs<i>) which falls below the reference reset voltage Vddr. Note that noise Vnoise<i> of the reset transistor MRS<i> is represented by Vktc<i>+Vft<i>.
Next, a power supply pulse φVdd<i+1> is set at reference clip voltage Vddc (<Vddr). Moreover, a reset pulse φRS<i+1> is changed to the high level, and a transfer pulse φTR<i+1> is changed to the low level. This allows FD part voltage Vfd<i+1> to be set at the reference clip voltage Vddc. In such a state, since the reference clip voltage Vddc is voltage for generating clip voltage, the reference clip voltage Vddc is set at voltage lower than the reference reset voltage Vddr by Va (Vddc=Vddr−Va).
Next, while the reset voltage is sampled and held due to high-brightness light, the FD part voltage Vfd<i> drops to the minimum voltage Vfdmin<i> permitted at the FD part. Accordingly, the pixel output voltage Vpixout<i> also drops.
Meanwhile, at the pixel 110<i+1>, the following state is brought about: the reset pulse φRS<i+1> is at the high level, the transfer pulse φTR<i+1> is at the low level, and Vdd<i+1>=Vddc. This allows the FD part voltage Vfd<i+1> to be set at the reference clip voltage Vddc. Thus, the pixel output voltage Vpixout does not fall below clip voltage Vc<i+1>(=Vddc−Vgs<i+1>). That is, the pixel output voltage Vpixout is clipped at the clip voltage Vc<i+1>.
Next, in order to transfer a charge signal, the voltage of the vertical signal line 111 is dropped. Thus, the power supply pulse φVdd<i+1> of the pixel 110<i+1> is set at the non-selected pixel voltage Vddl, the clamp pulse φCL is changed to the low level, and the reset pulse φRS<i+1> is maintained at the high level.
Next, the transfer pulse φTR<i> of the pixel 110<i> is changed to the high level, and signal voltage is transferred as the pixel output voltage Vpixout<i>. In such a state, since the power supply pulse φVdd<K> and the power supply pulse φVdd<i+1> are both set at the non-selected pixel voltage Vddl, only the FD part voltage Vfd<i> of the pixel 110<i> is output as the pixel output voltage Vpixout<i>.
Subsequently, in order to read signals from a subsequent row, the power supply pulse φVdd<i+1> of the pixel 110<i+1> is set at the reference reset voltage Vddr. Then, the similar operation described above is performed to read a signal from the pixel 110<i+1> with a pixel 110<i+2> being used as a clipping pixel.
The foregoing operation is sequentially performed for each of the pixels arranged in an array pattern, thereby obtaining an image for which the blocked-up shadows are reduced. That is, when high-brightness light enters, no blocked-up shadows occur even if the pixel output voltage Vpixout<i> drops. When the pixel output voltage is Vpixout(sig)<i>, signal voltage of (Vc<i+1>−Vpixout(sig)<i>) can be obtained by the CDS circuit 113.